Semiconductor devices are used in a variety of electronic applications, such as personal computers, cell phones, digital cameras, and other electronic equipment, as examples. The semiconductor industry continues to improve the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by continual reductions in minimum feature size, which allow more components to be integrated into a given area. These smaller electronic components also require smaller packages that utilize less area than packages of the past, in some applications.
One type of smaller packaging for semiconductor devices that has been developed is wafer level packaging (WLP), in which integrated circuit die are packaged in packages that typically include a redistribution layer (RDL) that is used to fan out wiring for contact pads of the integrated circuit die so that electrical contact can be made on a larger pitch than contact pads of the die. Throughout this description, the term die is used to refer to both the singular and the plural.
WLP packages have been applied more and more in integrated circuit packaging due to the advantages of cost and simple structure. However, for some WLP packages, stress has been found to be directly applied on passivation (PSV) and extreme low-k (ELK) layers, causing ELK/PSV crack/delamination by severe fatigue loading during reliability testing.